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| SigmaTel, Inc. Integrating Mixed-Signal Solutions Multimedia Audio Codec for AC'97 STAC9704/7 GENERAL DESCRIPTION: SigmaTel's STAC9704/07 is a general purpose 18-bit, full duplex, audio codec that conforms to the analog component specification of AC'97 (Audio Codec '97 Component Specification rev. 1.03). The STAC9704/07 incorporates SigmaTel's proprietary Sigma-Delta technology to achieve signal quality in excess of 95dB SNR. The DACs, ADCs, and mixers are integrated with analog I/Os, which include four analog line-level stereo inputs, two analog line-level mono inputs, and 3 output channels. Also included are SigmaTel's 3D stereo enhancement (SS3D) and an extra true line-level out for headphones or speaker amplifiers. The STAC9704/07 communicates via the five wire AC Link to any digital component of AC'97 providing flexibility in the audio system design. Packaged in a small AC'97 compliant 48-pin TQFP, the STAC9704/07 can be placed on the motherboard, daughter boards, add-on cards, PCMCIA cards, or outside the main chassis such as in a speaker. The 9707 is identical to the 9704 except that the 9707 is tested at AVdd = DVdd = 3.3V. FEATURES: * * * * * * High performance technology 18-bit full duplex stereo A/D, D/A AC-link protocol compliance Single power source from 5V to 3.3V AC'97 compliant mixer SigmaTel Surround (SS3D) Stereo Enhancement * * * * * * Energy saving power down modes 48k sample/second rate Six analog line-level inputs 48-pin TQFP SNR > 95 dB through Mixer and DAC STAC9707 is the 3.3 volt version 1 10/02/98 ORDERING INFORMATION: PART NUMBER STAC9704T STAC9707T PACKAGE 48-pin TQFP 7mm x 7mm x 1.4mm 48-pin TQFP 7mm x 7mm x 1.4mm TEMPERATURE RANGE 0o C to +70o C 0o C to +70o C SUPPLY RANGE DVdd = 3.3V - 5V, AVdd = 5V DVdd = 3.3V AVdd = 3.3V SigmaTel reserves the right to change specifications without notice. 2 10/02/98 SigmaTel, Inc Table of Contents General Description Ordering Information 1. PIN/SIGNAL Descriptions 1.1 Digital I/O 1.2 Analog I/O 1.3 Filter and Voltage References 1.4 Power and Ground Signals 2. AC-Link 2.1 Clocking 2.2 Reset 3. Digital Interface 3.1 AC-link Digital Serial Interface Protocol 3.1.1 AC-link Audio Output Frame (SDATA_OUT) 3.1.1.1 Slot 1: Command Address Port 3.1.1.2 Slot 2: Command Data Port 3.1.1.3 Slot 3: PCM Playback Left Channel 3.1.1.4 Slot 4: PCM Playback Right Channel 3.1.1.5 Slots 5-12: Reserved. 3.1.2 AC-link Audio Input Frame (SDATA_IN) 3.1.2.1 Slot 1: Status Address Port 3.1.2.2 Slot 2: Status Data Port 3.1.2.3 Slot 3: PCM Record Left Channel 3.1.2.4 Slot 4: PCM Record Right Channel 3.1.2.5 Slots 5-12: Reserved 3.2 AC-link Low Power Mode 3.2.1 Waking up the AC-Link 1 2 8 8 9 10 11 11 12 12 12 12 STAC9704/7 4. STAC9704/7 Mixer 4.1 Mixer Input. 4.2 Mixer Output 4.3 PC Beep Implementations 4.4 Mixer Registers 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 Reset Register Play Master Volume Registers PC Beep Register Analog Mixer Input Gain Record Select Control Record Gain Registers General Purpose Register 3D Control Register Powerdown Control/Status 21 23 23 23 24 25 25 25 26 26 28 28 29 29 30 32 32 32 33 34 35 36 36 37 38 38 38 39 39 40 42 44 45 5. Low Power Modes 6. Testability 7. AC Timing Characteristics 7.1 Cold Reset. 7.2 Warm Reset 7.3 Clocks 7.4 Data Setup and Hold 7.5 Signal Rise and Fall Times 7.6 AC-link Low Power Mode Timing 7.7 ATE Test Mode 8. Electrical Specifications 8.1 Absolute Maximum Ratings 8.2 Recommended Operating Conditions 8.3 Power Consumption 8.4 AC link Static Digital Specifications 8.5 9704 Analog Performance Characteristics 8.6 9707 Analog Performance Characteristics APPENDIX A APPENDIX B 14 16 16 16 17 17 17 19 19 19 19 20 20 21 3 10/02/98 SigmaTel, Inc Table of Contents - Tables Table 1 - Package Dimensions Table 2 - Pin Designation Table 3 - Digital Signal List Table 4 - Analog Signal List Table 5 - Filtering and Voltage References Table 6 -Power Signal List STAC9704/07 Table 7 Table 8 - Mixer Functional Connections Table 9 - Mixer Registers Table 10 - Play Master Volume Register Table 11 - PC Beep Register Table 12 - Analog Mixer Input Gain Register Table 13 - Record Select Control Registers Table 14 - Record Gain Registers Table 15 - General Purpose Register Table 16 - 3D Control Register Table 17 - Powerdown Status Register Table 18 - Low Power Modes Table 19 - Cold Reset Table 20 - Warm Reset Table 21 - Clocks Table 22 - Data Setup and Hold Table 23 - Signal Rise and Fall Times Table 24 - AC-link Low Power Mode Timing Table 25 - ATE Test Mode Table 26 - Operating Conditions Table 27 - Power Consumption 38 39 4 STAC9704/7 Table 28 - AC-link Static Specifications 5 5 8 9 10 11 Table 29 - 9704 Analog Performance Characteristics Table 30 - 9707 Analog Performance Characteristics 39 40 42 Table of Contents - Figures Figure 1 - Package Outline Figure 2 - STAC9704 Block Diagram Figure 3 - Connection Diagram 5 6 7 11 14 15 15 18 18 20 22 24 25 26 26 27 28 28 29 30 30 32 33 34 35 36 37 37 Figure 4 - STAC9704/07 AC'97 Link Figure 5 - AC'97 Bi-directional Audio Frame Figure 6 - AC-link Audio Output Frame Figure 7 - Start of an Audio Output Frame Figure 8 - STAC9704/07 Audio Input Frame Figure 9 - Start of an Audio Input Frame Figure 10 - STAC9704 Powerdown Timing Figure 11 - STAC9704/07 Mixer Functional Diagram 22 Figure 12 - Example of STAC9704/07 Powerdown/ Powerup flow Figure 13 - STAC9704/07 Powerdown/Powerup with analog still alive Figure 14 - Cold Reset Figure 15 - Warm Reset Figure 16 - Clocks Figure 17 - Data Setup and Hold Figure 18 - Signal Rise and Fall Times Figure 19 - AC-link Low Power Mode Timing Figure 20 - ATE Test Mode 31 31 32 33 34 35 36 36 37 10/02/98 SigmaTel, Inc Figure 1 - Package Outline D D1 STAC9704/7 Table 1 - Package Dimensions KEY 26 a 38 SigmaTel E E1 e STAC9704/7 48 pin TQFP 14 2 D D1 E E1 a (lead width) e (pitch) thickness 9704/7 DIMENSION TQFP 9.00 mm 7.00 mm 9.00 mm 7.00 mm 0.20 mm 0.50 mm 1.4 mm Table 2 - Pin Designation PIN # 1 2 3 4 5 6 7 8 9 10 11 12 SIGNAL NAME DVdd1 XTL_IN XTL_OUT DVss1 SDATA_OUT BIT_CLK DVss2 SDATA_IN DVdd2 SYNC RESET# PC_BEEP PI N# 13 14 15 16 17 18 19 20 21 22 23 24 SIGNAL NAME PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R PIN # 25 26 27 28 29 30 31 32 33 34 35 36 SIGNAL NAME AVdd1 AVss1 Vref Vrefout AFILT1 AFILT2 NC CAP2 NC NC LINE_OUT_L LINE_OUT_R PIN # 37 38 39 40 41 42 43 44 45 46 47 48 SIGNAL NAME MONO_OUT AVdd2 LNLVL_OUT_L NC LNLVL_OUT_R AVss2 NC NC NC NC NC NC # denotes active low 5 10/02/98 SigmaTel, Inc. Figure 2. STAC9704 Block Diagram 2 mono sources 4 stereo sources Power Management PCM out DACs 48Kss Digital STAC9704/7 mono stereo LNLVL_OUT MIXER Analog mixing DAC DAC AC-link SYNC BIT_CLK SDATA_OUT SDATA_IN RESET Interface LINE_OUT MONO_OUT Registers 64 x 16 bits PCM in ADCs ADC ADC 48Kss and Gain control Mic Boost 0/20 dB M U X MIC1 MIC2 The STAC9704/7 block diagram, above, illustrates its primary functional blocks. It performs fixed 48K sample rate D-A & A-D conversion, mixing, and analog processing. The digital interface communicates with the AC'97 controller via the five wire AC-link and contains the 64 word by 16-bit registers. Two fixed 48Kss DAC's support a stereo PCM-out channel which contains a mix generated in the AC'97 controller of all software sources, including the internal synthesizer and any other digital sources. The Mixer block mixes the PCM-out with any analog sources, then outputs to LINE_OUT and LNLVL_OUT. The MONO_OUT delivers either mic only or a mono mix of sources from the mixer. The two fixed 48Ks ADC's take any mix of mono or stereo sources, and convert it to a stereo PCM-in signal. All ADCs and DACs operate at 18-bit resolution. The STAC9704/7 is designed primarily to support stereo, 2-speaker PC audio. However, multi-channel encoded stereo can be played out through the LINE_OUT and LNLVL_OUT. This encoded signal can be played on normal stereo speakers, or sent to consumer equipment or other decoding devices via LINE_OUT and LNLVL_OUT to an analog input connection for multi-channel playback. As an option, the STAC9704/07 provides for a stereo enhancement feature, Sigmatel Surround 3D (SS3D). SS3D provides the listener with several options to expand the soundstage beyond the normal 2-speaker arrangement. Together with the logic component (controller) of AC'97, STAC9704/7 can be SoundBlaster(R) and Windows(R) Sound System compatible. SoundBlaster(R) is a registered trademark of Creative Labs. Windows(R) is a registered trademark of Microsoft Corporation. 6 10/02/98 SigmaTel, Inc. STAC9704/7 Figure 3 - Connection Diagram - See Appendix A for an alternative connection diagram when using separate supplies. See Appendix B for specific connection requirements prior to operation. 2 ohm * Ferrite Bead * * Suggested 3.3V or 5V +/-10% 0.1uF 0.1uF 10uF 0.1uF 38 AVdd2 1 DVdd1 10uF 0.1uF 25 AVdd1 12 9 DVdd2 2 33pF PC B EE P 13 PHONE 14 AUX_L _ XTL_IN 24.576MHz XTL_OUT 3 33pF 5 SDATA_OUT 15 AUX_R 16 VIDEO_L SIGMATEL 6 BIT_CLK 8 SDATA_IN 10 17 VIDEO_R 18 CD_L S T A C 9 7 0 4 /7 SYNC 11 RESET 27 Vref 0.1uF 28 10uF 19 CD_GND 20 CD_R 21 MIC1 22 MIC2 23 35 CAP2 Vrefout 32 0.1uF 10uF LINE_IN_L 24 LINE_OUT_L LINE_IN_R LINE_OUT_R 560 to 1000 pF 29 560 to 1000 pF 30 AFILT2 AFILT1 36 37 MONO_OUT AVss1 26 AVss2 42 DVss1 4 DVss2 7 LNLVL_OUT_L LNLVL_OUT_R 39 41 ** Teminate ground plane as close to power supply as possible NOTE: Pins 31, 33, 34, 40, 43 - 48 are No Connects Brd Analog Gnd Brd Digital Gnd 7 10/02/98 SigmaTel, Inc. 1. PIN/SIGNAL DESCRIPTIONS 1.1 Digital I/O STAC9704/7 These signals connect the STAC9704/7 to its AC'97 controller counterpart and an external crystal. Table 3. Digital Signal List SIGNAL NAME RESET # XTL_IN XTL_OUT SYNC BIT_CLK SDATA_OUT SDATA__IN # denotes active low TYPE I I O I O I O DESCRIPTION AC'97 Master H/W Reset 24.576 MHz Crystal 24.576 MHz Crystal 48 kHz fixed rate sample sync 12.288 MHz serial data clock Serial, time division multiplexed, AC'97 input stream Serial, time division multiplexed, AC'97 output stream 8 10/02/98 SigmaTel, Inc. 1.2 Analog I/O STAC9704/7 These signals connect the STAC9704/7 to analog sources and sinks, including microphones and speakers. Table 4. Analog Signal List SIGNAL NAME PC-BEEP PHONE MIC1 MIC2 LINE-IN-L LINE-IN-R CD-L CD-GND CD-R VIDEO-L VIDEO-R AUX-L AUX-R LINE-OUT-L LINE-OUT-R MONO-OUT TYPE I I I I I I I I I I I I I O O O DESCRIPTION PC Speaker beep pass through From telephony subsystem speakerphone (or DLP - Down Line Phone) Desktop Microphone Input Second Microphone Input Line In Left Channel Line In Right Channel CD Audio Left Channel CD Audio analog ground CD Audio Right Channel Video Audio Left Channel Video Audio Right Channel Aux Left Channel Aux Right Channel Line Out Left Channel Line Out Right Channel To telephony subsystem speakerphone (or DLP - Down Line Phone) 9 10/02/98 SigmaTel, Inc. LNLVL_OUT_L LNLVL_OUT_R O O STAC9704/7 True Line Level Out Left Channel True Line Level Out Right Channel * Note: any unused input pins should have a capacitor (1 uF suggested) to ground. 1.3 Filter and Voltage References These signals are connected to resistors, capacitors, or specific voltages. Table 5. Filtering and Voltage References SIGNAL NAME Vref Vrefout AFILT1 AFILT2 CAP2 TYPE O O O O O DESCRIPTION Reference Voltage Reference Voltage out 5mA drive (intended for mic bias) Anti-Aliasing Filter Cap - ADC channel Anti-Aliasing Filter Cap - ADC channel ADC reference Cap 10 10/02/98 SigmaTel, Inc. 1.4 Power and Ground Signals Table 6. Power Signal List STAC9704/7 STAC9704/7 SIGNAL NAME AVdd1 AVdd2 AVss1 AVss2 DVdd1 DVdd2 DVss1 DVss2 TYPE I I I I I I I I STAC9704 Analog Vdd = 5.0V Analog Vdd = 5.0V Analog Gnd Analog Gnd Digital Vdd = 5.0V or 3.3V Digital Vdd = 5.0V or 3.3V Digital Gnd Digital Gnd STAC9707 Analog Vdd = 3.3V Analog Vdd = 3.3V Analog Gnd Analog Gnd Digital Vdd = 3.3V Digital Vdd = 3.3V Digital Gnd Digital Gnd 2. AC-LINK Below is the figure of the AC-link point to point serial interconnect between the STAC9704/7 and its companion controller. All digital audio streams and command/status information are communicated over this AC-link. Please refer to the "Digital Interface" section 3 for details. Figure 4. STAC9704/7's AC97-link to its companion controller SYNC XTAL_IN Digital DC'97 Controller BIT_CLK SDATA_OUT SDATA_IN STAC9704/7 XTAL_OUT RESET 11 10/02/98 SigmaTel, Inc. 2.1 Clocking STAC9704/7 STAC9704/7 derives its clock internally from an externally connected 24.576 MHz crystal or an oscillator through the XTAL_IN pin. Synchronization with the AC'97 controller is achieved through the BIT_CLK pin at 12.288 MHz (half of crystal frequency). The beginning of all audio sample packets, or "Audio Frames", transferred over AC-link is synchronized to the rising edge of the "SYNC" signal driven by the AC'97 controller. Data is transitioned on AC-link on every rising edge of BIT_CLK, and subsequently sampled by the receiving side on each immediately following falling edge of BIT_CLK. 2.2 Reset There are 3 types of resets as detailed under "Timing Characteristics". 1. 2. 3. a "cold" reset where all STAC9704/7 logic and registers are initialized to their default state a "warm" reset where the contents of the STAC9704/7 register set are left unaltered a "register" reset which only initializes the STAC9704/7 registers to their default states After signaling a reset to the STAC9704/7, the AC'97 controller should not attempt to play or capture audio data until it has sampled a "Codec Ready" indication via register 26h from the STAC9704/7. For proper reset operation, SDATA_OUT should be "0" during "cold" reset. 3. DIGITAL INTERFACE 3.1 AC-link Digital Serial Interface Protocol The STAC9704/7 communicates to the AC'97 controller via a 5 pin digital serial interface called AClink, which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams, commands and status information are communicated over this point to point serial interconnect. This link handles multiple inputs, and output audio streams, as well as control register accesses using a time division multiplexed (TDM) scheme. The AC'97 controller synchronizes all AC-link data transaction. The following data streams are available on the STAC9704/7: 12 10/02/98 SigmaTel, Inc. * * * * PCM Playback PCM Record data Control Status 2 output slots 2 input slots 2 output slots 2 input slots STAC9704/7 2 Channel composite PCM output stream 2 Channel composite PCM input stream Control register write port Control register read port Synchronization of all AC-link data transactions is signaled by the AC'97 controller. The STAC9704/7 drives the serial bit clock onto AC-link. The AC'97 controller then qualifies with a synchronization signal to construct audio frames. SYNC, fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AClink data, STAC9704/7 for outgoing data and AC'97 controller for incoming data, samples each serial bit on the falling edges of BIT_CLK. The AC-link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit positions) time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A "1" in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is "tagged" invalid, it is the responsibility of the source of the data, (STAC9704/7 for the input stream, AC'97 controller for the output stream), to stuff all bit positions with 0's during that slot's active time. SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the "Tag Phase". The remainder of the audio frame where SYNC is low is defined as the "Data Phase". Additionally, for power savings, all clock, sync, and data signals can be halted. Figure 5. AC'97 Standard Bi-directional Audio Frame SLOT # 0 1 2 3 4 5 6 7 8 9 10 11 12 SYNC OUTGOING STREAMS INCOMING STREAMS TAG PHASE DATA PHASE TAG CMD ADR CMD PCM DATA LEFT PCM RT PCM RT NA RSVD RSVD RSVD RSVD RSVD RSVD RSVD STATUS STATUS PCM TAG ADR DATA LEFT NA NA RSVD RSVD RSVD RSVD RSVD RSVD 13 10/02/98 SigmaTel, Inc. 3.1.1 AC-link Audio Output Frame (SDATA_OUT) STAC9704/7 The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the STAC9704/7 DAC inputs, and control registers. Each audio output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-link protocol infrastructure. Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the entire audio frame. If the "Valid Frame" bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12 bit positions sampled by the STAC9704/7 indicate which of the corresponding 12 times slots contain valid data. In this way data streams of differing sample rates can be transmitted across AC-link at its fixed 48kHz audio frame rate. The following diagram illustrates the time slot based AC-link protocol. Figure 6. AC-link Audio Output Frame Data Phase Tag Phase 20.8 uS (48 kHZ) SYNC BIT_CLK 12.288 MHz SDATA_OUT valid Frame slot1 slot2 slot(12) "0" "0" "0" 19 "0" 19 "0" 19 "0" 19 "0" End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12 A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the STAC9704/7 samples the assertion of SYNC. This following edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, the AC'97 controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the STAC9704/7 on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. 14 10/02/98 SigmaTel, Inc. Figure 7: Start of an Audio Output Frame STAC9704/7 STAC9701 samples SYNC assertion here SYNC STAC9701 samples first SDATA_OUT bit of frame here BIT_CLK valid Frame SDATA_OUT slot1 slot2 End of previous audio frame SDATA_OUT's composite stream is MSB justified (MSB first) with all non-valid slots' bit positions stuffed with 0's by the AC'97 controller When mono audio sample streams are sent from the AC'97 controller, it is necessary that BOTH left and right sample stream time slots be filled with the same data. 3.1.1.1 Slot 1: Command Address Port The command port is used to control features, and monitor status (see Audio Input Frame Slots 1 and 2) of the STAC9704/7 functions including, but not limited to, mixer settings, and power management (refer to the control register section of this specification). The control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid. Audio output frame slot 1 communicates control register address, and write/read command information to the STAC9704/7. Command Address Port bit assignments: Bit (19) Read/Write command (1= read, 0=write) Bit (18:12) Control Register Index (64 16-bit locations, addressed on even byte boundaries) Bit (11:0) Reserved (Stuffed with 0's) The first bit (MSB) sampled by STAC9704/7 indicates whether the current control transaction is a read or a write operation. The following 7 bit positions communicate the targeted control register address. The trailing 12 bit positions within the slot are reserved and must he stuffed with 0's by the AC'97 controller. 15 10/02/98 SigmaTel, Inc. 3.1.1.2 Slot 2: Command Data Port STAC9704/7 The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle. (as indicated by Slot 1, bit 19) Bit (19:4) Bit (3 :0) Control Register Write Data (Stuffed with 0's if current operation is a read) Reserved (Stuffed with 0's) If the current command port operation is a read then the entire slot time must be stuffed with 0's by the AC'97 controller. 3.1.1.3 Slot 3: PCM Playback Left Channel Audio output frame slot 3 is the composite digital audio left playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's. 3.1.1.4 Slot 4: PCM Playback Right Channel Audio output frame slot 4 is the composite digital audio right playback stream. In a typical "Games Compatible" PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC'97 controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC'97 controller must stuff all trailing non-valid bit positions within this time slot with 0's. 3.1.1.5 Slots 5-12: Reserved Audio output frame slots 5-12 are reserved for future use and are always stuffed with 0's by the AC'97 controller. 3.1.2 AC-link Audio Input Frame (SDATA_IN) The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC'97 controller. As is the case for audio output frame, each AC-link audio input frame consists of 12, 20-bit time slots. Slot 0 is a special reserved time slot containing 16 bits that are used for AC-link protocol infrastructure. 16 10/02/98 SigmaTel, Inc. STAC9704/7 Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the STAC9704/7 is in the "Codec Ready" state or not. If the "Codec Ready" bit is a 0, this indicates that STAC9704/7 is not ready for normal operation. This condition is normal following the de-assertion of power on reset, for example, while STAC9704/7's voltage references settle. When the AC-link "Codec Ready" indicator bit is a 1, it indicates that the AC-link and STAC9704/7 control/status registers are in a fully operational state. The AC'97 controller must further probe the Powerdown Control Status Register (refer to Mixer Register section) to determine exactly which subsections, if any, are ready. Prior to any attempts at putting STAC9704/7 into operation the AC'97 controller should poll the first bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that STAC9704/7 has become "Codec Ready". Once the STAC9704/7 is sampled "Codec Ready", the next 12 bit positions sampled by the AC'97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. The following diagram illustrates the time slot based AC-link protocol. Figure 8: STAC9704/7 Audio Input Frame Data Phase Tag Phase 20.8 uS (48 kHZ) SYNC BIT_CLK 12.288 MHz SDATA_IN valid Frame slot1 slot2 slot(12) "0" "0" "0" 19 "0" 19 "0" 19 "0" 19 "0" End of previous audio frame Time Slot "Valid" Bits ("1" = time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12 A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, STAC9704/7 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the STAC9704/7 transitions SDATA_IN into the first bit position of slot 0 ("Codec Ready" bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK and subsequently sampled by the AC'97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. 17 10/02/98 SigmaTel, Inc. STAC9704/7 Figure 9: Start of an Audio Input Frame STAC9704 samples SYNC assertion here SYNC STAC9704 samples first SDATA_OUT bit of frame here BIT_CLK Codec Ready SDATA_IN slot1 slot2 End of previous audio frame SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0's by STAC9704/7. SDATA_IN data is sampled on the falling edges of BIT_CLK. 3.1.2.1 Slot 1: Status Address Port The status port is used to monitor status for STAC9704/7 functions including, but not limited to, mixer settings, and power management. Audio input frame slot 1's stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged "valid" by STAC9704/7 during slot 0) Status Address Port hit assignments: Bit (19) RESERVED (Stuffed with 0) Bit (18;12) Control Register Index (Echo of register index for which data is being returned) Bit (11:0) RESERVED (Stuffed with 0's) The first bit (MSB) generated by STAC9704/7 is always stuffed with a 0. The following 7 bit positions communicate the associated control register address, and the trailing 12 bit positions are stuffed with 0's by STAC9704/7. 18 10/02/98 SigmaTel, Inc. 3.1.2.2 Slot 2: Status Data Port The status data port delivers 16-bit control register read data. Bit (19:4) Bit (3 :0) Control Register Read Data RESERVED STAC9704/7 (Stuffed with 0's if tagged "invalid") (Stuffed with 0's) If Slot 2 is tagged "invalid" by STAC9704/7, then the entire slot will be stuffed with 0's. 3.1.2.3 Slot 3: PCM Record Left Channel Audio input frame slot 3 is the left channel output of STAC9704/7 input MUX, post-ADC. STAC9704/7 ADCs are implemented to support 18-bit resolution. STAC9704/7 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. 3.1.2.4 Slot 4: PCM Record Right Channel Audio input frame slot 4 is the right channel output of STAC9704/7 input MUX, post-ADC. STAC9704/7 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. 3.1.2.5 Slots 5-12: Reserved Audio input frame slots 5-12 are reserved for future use and are always stuffed with 0's. 3.2 AC-link Low Power Mode The STAC9704/7's AC-Link can be placed in the low power mode by programming Register 26h to the appropriate value. SDATA_IN is held at a logic low voltage level. The BIT_CLK is held at logic high after slot 2, in violation of the AC97 specification. This issue is detailed in the STAC9704 errata, and has not caused customer problems. The AC'97 controller can wake up the STAC9704/7 by providing the appropriate reset signals. 19 10/02/98 SigmaTel, Inc. Figure 10. STAC9704/7 Powerdown Timing STAC9704/7 SYNC BIT_CLK slot2 per frame TAG Write to 0x20 Data PR4 SDATA_OUT SDATA_IN slot2 per frame TAG Note: BIT_CLK not to scale BIT_CLK and SDATA_IN are transitioned low immediately (within the maximum specified time) following the decode of the write to the Powerdown Register (26h) with PR4. When the AC'97 controller driver is at the point where it is ready to program the AC-link into its low power mode, slots (1 and 2) are assumed to be the only valid stream in the audio output frame (all sources of audio input have been neutralized). The AC'97 controller should also drive SYNC, and SDATA_OUT low after programming the STAC9704/7 to this low power mode. 3.2.1 Waking up the AC-link Once the STAC9704/7 has halted BIT_CLK, there are only two ways to "wake up" the AC-link. Both methods must be activated by the AC'97 controller. The AC-link protocol provides for a "Cold AC'97 Reset", and a "Warm AC'97 Reset". The current power down state would ultimately dictate which form of reset is appropriate. Unless a "cold" or "register" reset (a write to the Reset register) is performed, wherein the AC'97 registers are initialized to their default values, registers will keep their current state during all power down modes. Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not occur for a minimum of 4 audio frame times following the frame in which the power down was triggered. When AC-link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit 15). 20 10/02/98 SigmaTel, Inc. STAC9704/7 Cold Reset - a cold reset is achieved by asserting RESET# for the minimum specified time. By driving RESET# low, BIT_CLK, and SDATA_IN will be activated, or re-activated as the case may be, and all STAC9704/7 control registers will be initialized to their default power on reset values. Note: RESET# is an asynchronous input. # denotes active low Warm Reset - a warm reset will re-activate the AC-link without altering the current STAC9704/7 register values. A warm reset is signaled by driving SYNC high for a minimum of 1 us in the absence of BIT_CLK. Note: Within normal audio frames, SYNC is a synchronous input. However, in the absence of BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the STAC9704/7. 21 10/02/98 SigmaTel, Inc. 4. STAC9704/7 MIXER STAC9704/7 The STAC9704/7 mixer is designed to the AC'97 specification to manage the playback and record of all digital and analog audio sources in the PC environment. These include: * * * * * * System Audio: digital PCM input and output for business, games and multimedia CD/DVD: analog CD/DVD-ROM Redbook audio with internal connections to Codec mixer Mono microphone: choice of desktop mic, with programmable boost and gain Speakerphone: use of system mic and speakers for telephone, DSVD, and video conferencing Video: TV tuner or video capture card with internal connections to Codec mixer AUX/synth: analog FM or wavetable synthesizer, or other internal source Figure 11. STAC9704/7 Mixer Functional Diagram PCM out D/A PC_Beep Phone MIC1 MIC2 LINE IN CD Video AUX 20dB vol vol vol vol vol vol vol vol mute mute mute mute mute mute mute mute 3D Analog Audio Sources -6dB LNLVL Volume Master Volume Mono Volume LNLVL_OUT 3D -6dB LINE_OUT MONO_OUT MUX KY E MonoAnalog StereoAnalog D igital MUX Master Input Volume A/D A/D PCM IN 22 10/02/98 SigmaTel, Inc. Table 8. Mixer functional connections STAC9704/7 SOURCE PC_Beep PHONE MIC1 MIC2 LINE_IN CD VIDEO AUX PCM out LINE_OUT LNLVL_OUT MONO_OUT PCM in FUNCTION PC beep pass thru speakerphone or DLP in desktop microphone second microphone external audio source audio from CD-ROM audio from TV tuner or video camera upgrade synth or other external source digital audio output from AC'97 Controller stereo mix of all sources Additional stereo mix of all sources mic or mix for speakerphone or DLP out digital audio input to AC'97 Controller CONNECTION from PC beeper output from telephony subsystem from mic jack from second mic jack from line-in jack cable from CD-ROM cable from TV or VidCap card internal connector AC-link To output jack To output jack to telephony subsystem AC-link 23 10/02/98 SigmaTel, Inc. 4.1 Mixer Input STAC9704/7 The mixer provides recording and playback of any audio sources or output mix of all sources. The STAC9704/7 supports the following input sources: * any mono or stereo source * mono or stereo mix of all sources * 2-channel input w/mono output reference (mic + stereo mix) Note: any unused input pins must have a capacitor (1 uF suggested) to ground. 4.2 Mixer Output The mixer generates two distinct outputs: * * * a stereo mix of all sources for output to the LINE_OUT a stereo mix of all sources for output to the LNLVL_OUT a mono, mic only or mix of all sources for MONO_OUT * Note: Mono output of stereo mix is attenuated by 6 dB. 4.3 PC Beep Implementation PC Beep is active on power up and defaults to an unmuted state. During active RESET#, PC_BEEP is passed through the codec to LINE_OUT. The user should mute this input before using any other mixer input because the PC Beep input can contribute noise to the lineout during normal operation. 24 10/02/98 SigmaTel, Inc. 4.4 Mixer Registers: Table 9. Mixer Registers STAC9704/7 REG # 00h 02h 04h 06h NAME Reset Master Volume LNLVL Volume D15 X Mute Mute D14 SE4 X X X X X X X X X X X X X X X PR6 0 1 D13 SE3 X X X X X X X X X X X X X 3D X PR5 0 1 D12 SE2 ML4 ML4 X X X X GL4 GL4 GL4 GL4 GL4 X X X X PR4 0 1 D11 SE1 ML3 ML3 X X X X GL3 GL3 GL3 GL3 GL3 X GL3 X X PR3 0 0 D10 SE0 ML2 ML2 X X X X GL2 GL2 GL2 GL2 GL2 SL2 GL2 X X PR2 0 1 D9 ID9 ML1 ML1 X X X X GL1 GL1 GL1 GL1 GL1 SL1 GL1 MIX X PR1 1 1 D8 ID8 ML0 ML0 X X X X GL0 GL0 GL0 GL0 GL0 SL0 GL0 MS X PR0 1 0 D7 ID7 X X X X X X X X X X X X X LPBK X X 1 0 D6 ID6 X X X X X 20dB X X X X X X X X X X 0 0 D5 ID5 X X X X X X X X X X X X X X X X 0 0 D4 ID4 MR4 MR4 MM4 PV3 GN4 GN4 GR4 GR4 GR4 GR4 GR4 X X X X X 0 0 D3 ID3 MR3 MR3 MM3 PV2 GN3 GN3 GR3 GR3 GR3 GR3 GR3 X GR3 X X REF 0 0 D2 ID2 MR2 MR2 MM2 PV1 GN2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 X X ANL 1 1 D1 ID1 MR1 MR1 MM1 PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 X DP1 DAC 0 0 D0 ID0 MR0 MR0 MM0 X GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 X DP0 ADC 0 0 DE FAULT NA 8000h 8000h 8000h 0000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 000Fh NA NA Master Volume Mute Mono 0Ah PC_BEEP Volume Mute 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 20h 22h 26h 7Ch 7Eh Phone volume Mic Volume Line In Volume CD Volume Video Volume AUX Volume Mute Mute Mute Mute Mute Mute PCM Out Volume Mute Record Select Record Gain General Purpose 3D Control Powerdown Ctrl/Stat Vendor ID1 Vendor ID2 X Mute X X PR7 1 0 Notes: 1. All registers not shown and bits containing an X are reserved. 2. Any reserved bits, marked X, can be written to but are don't care upon read back. 3. PC_BEEP default to 0000h, mute off. 4. If optional bits D13, D5 of register 02H or D5 of register 06h are set to 1, then the corresponding attenuation is set to 46dB and the register reads will produce 3Fh as a value for this attenuation/gain block. 25 10/02/98 SigmaTel, Inc. 4.4.1 Reset Register (Index 00h) STAC9704/7 Writing any value to this register performs a register reset, which causes all registers to revert to their default values. Reading this register returns the ID code of the part. 4.4.2 Play Master Volume Registers (Index 02h, 04h, and 06h) These registers manage the output signal volumes. Register 02h controls the stereo master volume (both right and left channels), register 04h controls the optional stereo true line level out, and register 06h controls the mono volume output. Each step corresponds to 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. ML5 through ML0 is for left channel level, MR5 through MR0 is for the right channel and MM5 through MM0 is for the mono out channel. The default value is 8000h (1000 0000 0000 0000), which corresponds to 0 dB attenuation with mute on. Table 10: Play Master Volume Register MUTE 0 0 1 Mx5...Mx0 00 0000 01 1111 xx xxxx FUNCTION 0dB Attenuation 46.5 Attenuation dB Attenuation RANGE Req. Req. Req. 4.4.3 PC Beep Register (Index 0Ah) This register controls the level for the PC Beep input. Each step corresponds to approximately 3 dB of attenuation. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. PC_BEEP supports motherboard implementations. The intention of routing PC_BEEP through the STAC9704/7 mixer is to eliminate the requirement for an onboard speaker by guaranteeing a connection to speakers connected via the output jack. In order for this to be viable the PC_BEEP signal needs to reach the output jack at all times. NOTE: the PC_BEEP is recommended to be routed to L & R Line outputs even when the STAC9704/7 is in a RESET state. This is so that Power On Self Test (POST) codes can be heard by the user in case of a hardware problem with the PC. For further PC_BEEP implementation details please refer to the AC'97 Technical FAQ sheet. The default value can be 0000h or 8000h, which corresponds to 0 dB attenuation with mute off or on. 26 10/02/98 SigmaTel, Inc. STAC9704/7 Table 11: PC_BEEP Register MUTE 0 0 1 PV3...PV0 0000 1111 xxxx FUNCTION 0 dB Attenuation 45 dB Attenuation dB Attenuation 4.4.4 Analog Mixer Input Gain Registers (Index 0Ch - 18h) These registers control the gain/attenuation for each of the analog inputs. Each step corresponds to approximately 1.5 dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB. Register 0Eh (Mic Volume Register) has an extra bit that is for a 20dB boost. When bit 6 is set to 1, the 20 dB boost is on. The default value is 8008, which corresponds to 0 dB gain with mute on. The default value for the mono registers is 8008h, which corresponds to 0dB gain with mute on. The default value for stereo registers is 8808h, which corresponds to 0 dB gain with mute on. Table 12: Analog Mixer Input Gain Register MUTE 0 0 0 1 Gx4...Gx0 00000 01000 11111 xxxxx FUNCTION +12 dB gain 0 dB gain -34.5 dB gain - dB gain 4.4.5 Record Select Control Register (Index 1Ah) Used to select the record source independently for right and left. The default value is 0000h, which corresponds to Mic in. 27 10/02/98 SigmaTel, Inc. STAC9704/7 Table 13: Record Select Control Registers SR2...SR0 0 1 2 3 4 5 6 7 RIGHT RECORD SOURCE Mic CD In (right) Video In (right) Aux In (right) Line In (right) Stereo Mix (right) Mono Mix Phone SL2...SL0 0 1 2 3 4 5 6 7 LEFT RECORD SOURCE Mic CD In (L) Video In (L) Aux In (L) Line In (L) Stereo Mix (L) Mono Mix Phone 28 10/02/98 SigmaTel, Inc. 4.4.6 Record Gain Registers (Index 1Ch) STAC9704/7 The 1Ch register adjusts stereo input record gain. Each step corresponds to 1.5 dB. 22.5 dB corresponds to 0F0Fh and 000Fh respectively. The MSB of the register is the mute bit. When this bit is set to 1, the level for that channel(s) is set at - dB. The default value is 8000h, which corresponds to 0 dB gain with mute on. Table 14: Record Gain Registers MUTE 0 0 1 GX3... GX0 1111 0000 xxxx FUNCTION +22.5 dB gain 0 dB gain - gain 4.4.7 General Purpose Register (Index 20h) This register is used to control some miscellaneous functions. Below is a summary of each bit and its function. The MS bit controls the mic selector. The LPBK bit enables loopback of the ADC output to the DAC input, without involving the AC-link, allowing for full system performance measurements. Table 15: General Purpose Register BIT 3D MIX MS LPBK FUNCTION 3D Stereo Enhancement on/off 1 = on Mono output select 0 = Mix, 1= Mic Mic select 0 = Mic1, 1 = Mic2 ADC/DAC loopback mode 29 10/02/98 SigmaTel, Inc. 4.4.8 3D Control Register (Index 22h) STAC9704/7 This register is used to control the 3D stereo enhancement function, Sigmatel Surround 3D (SS3D), built into the AC'97 component. Note the register bits, DP1 - DP0, are used to control the separation ratios in the 3D control. SS3D provides for a wider soundstage extending beyond the normal 2-speaker arrangement. Note that the 3D bit in the general purpose register (20h) must be set to 1 to enable SS3D functionality and for the bits in 22h to take effect. Table 16: 3D Control Registers DP1 - DP0 SEPARATION RATIO 00 01 10 11 3 (Default) 3 (Low) 4.5 (Med.) 6 (High) 3 separation ratios are implemented as shown above. The separation ratio defines a series of equations that determine the amount of depth difference (High, Medium, and Low) perceived during two-channel playback. The ratios provide for options to narrow or widen the soundstage. 4.4.9 Powerdown Control/Status Register (Index 26h) This read/write register is used to program powerdown states and monitor subsystem readiness. The lower half of this register is read only status, a "1" indicating that the subsection is "ready". Ready is defined as the subsection's ability to perform in its nominal state. When this register is written, the bit values that come in on AC-link will have no effect on read only bits 0-7. When the AC-link "Codec Ready" indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-link and AC'97 control and status registers are in a fully operational state. The AC'97 controller must further probe this Powerdown Control/Status Register to determine exactly which subsections, if any are ready. 30 10/02/98 SigmaTel, Inc. STAC9704/7 Table 17: Powerdown Status Register BIT REF ANL DAC ADC FUNCTION VREF's up to nominal level Analog mixers, etc. ready DAC section ready to playback data ADC section ready to playback data 5. LOW POWER MODES The STAC9704/7 is capable of operating at reduced power when no activity is required. The state of power down is controlled by the Powerdown Register (26h). There are 7 commands of separate power down. The power down options are listed in Table 18. The first three bits , PR0..PR2, can be used individually or in combination with each other, and control power distribution to the ADC's, DAC's and Mixer. The last analog power control bit, PR3, affects analog bias and reference voltages, and can only be used in combination with PR1, PR2, and PR3. PR3 essentially removes power from all analog sections of the codec, and is generally only asserted when the codec will not be needed for long periods. PR0 and PR1 control the PCM ADC's and DAC's only. PR2 and PR3 do not need to be "set" before a PR4, but PR0 and PR1 must be "set" before PR4. Table 18: Low Power Modes GRP BITS PR0 PR1 PR2 PR3 PR4 PR5 FUNCTION PCM in ADC's & Input Mux Powerdown PCM out DACs Powerdown Analog Mixer powerdown (Vref still on) Analog Mixer powerdown (Vref off) Digital Interface (AC-link) powerdown (extnl clk off) Internal Clk disable 31 10/02/98 SigmaTel, Inc. PR6 Not implemented STAC9704/7 Figure 12: Example of STAC9704/7 Powerdown/Powerup flow PR0=1 PR1=1 PR2=1 PR4=1 Normal PR0=0 & ADC=1 ADCs off PR0 PR1=0 & DAC=1 DACs off PR1 Analog off PR2 or PR3 PR2=0 & ANL=1 Digital I/F off PR4 Warm Reset Shut off Coda-link Ready =1 Default Cold Reset The above figure illustrates one example procedure to do a complete powerdown of STAC9704/7. From normal operation, sequential writes to the Powerdown Register are performed to power down STAC9704/7 a piece at a time. After everything has been shut off, a final write (of PR4) can be executed to shut down the AC-link. The part will remain in sleep mode with all its registers holding their static values. To wake up, the AC'97 controller will send an extended pulse on the sync line, issuing a warm reset. This will restart the AC-link (resetting PR4 to zero). The STAC9704/7 can also be woken up with a cold reset. A cold reset will reset all of the registers to their default states. When a section is powered back on, the Powerdown Control/Status register (index 26h) should be read to verify that the section is ready (stable) before attempting any operation that requires it. Figure 13: STAC9704/7 Powerdown/Powerup flow with analog still alive PR0=1 ADCs off PR0 PR0=0 & ADC=1 PR1=0 & DAC=1 PR1=1 PR4=1 Shut off Coda-link Normal DACs off PR1 Digital I/F off PR4 Warm Reset The above figure illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. This configuration can be used when playing a CD (or external LINE_IN source) through STAC9704/7 to the speakers, while most of the system in low power mode. The procedure for this follows the previous except that the analog mixer is never shut down. 32 10/02/98 SigmaTel, Inc. 6. TESTABILITY STAC9704/7 The STAC9704/7 has two test modes. One is for ATE in-circuit test and the other is restricted for SigmaTel's internal use. STAC9704/7 enters the ATE in circuit test mode if SDATA_OUT is sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-link outputs (BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of the AC'97 controller. This case will never occur during standard operating conditions. Once either of the two test modes have been entered, the STAC9704/7 must be issued another rest with all AC-link signals held low to return to the normal operating mode. 33 10/02/98 SigmaTel, Inc. 7. AC TIMING CHARACTERISTICS STAC9704/7 (Tambient = 25 C, AVdd = DVdd = 5.0V or 3.3V 5%, AVss=DVss+0V; 50pF external load) 7.1 Cold Reset Figure 14: Cold Reset Trst2clk Tres_low RESET# BIT_CLK Table 19 : Cold Reset PARAMETER RESET# active low pulse width RESET# inactive to BIT_CLK startup delay # denotes active low. SYMBOL Tres_low Trst2clk MIN 1.0 162.8 TYP MAX UNITS us ns 7.2 Warm Reset As per the STAC9704 errata, the BIT_CLK is triggered on the rising edge of the SYNC pulse rather than the falling edge of the SYNC pulse as specified in the AC97 specification. This issue is not known to have caused any customer problems. Figure 15: Warm Reset Tsync_high SYNC BIT_CLK Tsync_2clk 34 10/02/98 SigmaTel, Inc. Table 20: Warm Reset STAC9704/7 PARAMETER SYNC active high pulse width SYNC inactive to BIT_CLK startup delay SYMBOL Tsync_high Tsync_2clk MIN 162.8 TYP 1.3 - MAX - UNITS us ns 7.3 Clocks Figure 16: Clocks Tclk_low BIT_CLK Tclk_high Tclk_period Tsync_low SYNC Tsync_high Tsync_period Table 21: Clocks PARAMETER BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BLT_CLK high pulsewidth (note 1) BIT_CLK low pulse width (note 1) SYNC frequency SYNC period SYNC high pulse width SYNC low_pulse width SYMBOL Tclk_period Tclk_high Tclk_low Tsync_period Tsync_high Tsync_low MIN 32.56 32.56 TYP 12.288 81.4 40.7 40.7 48.0 20.8 1.3 19.5 MAX 750 48.84 48.84 UNITS MHz ns ps ns ns kHz us us us Notes: 1) Worst case duty cycle restricted to 40/60. 35 10/02/98 SigmaTel, Inc. 7.4 Data Setup and Hold (50pF external load) Figure 17: Data Setup and Hold STAC9704/7 Tsetup BIT_CLK SDATA_IN SDATA_OUT Thold SYNC Tsetup Thold Table 22: Data Setup and Hold PARAMETER Setup to falling edge of BIT_CLK Hold from falling edge of BIT_CLK SYMBOL Tsetup Thold MIN 15.0 5.0 TYP - MAX - UNITS ns ns Note 1: Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller. 36 10/02/98 SigmaTel, Inc. STAC9704/7 7.5 Signal Rise and Fall Times - (50pF external load; from 10% to 90% of Vdd) Figure 18: Signal Rise and Fall Times BIT_CLK Triseclk Tfallclk SDATA_IN Trisedin Tfalldin Table 23: Signal Rise and Fall Times PARAMETER BIT_CLK rise time BIT_CLK fall time SDATA_IN rise time SDATA_IN fall time SYMBOL Triseclk Tfallclk Trisedin Tfalldin MIN 2 2 2 2 TYP - MAX 6 6 6 6 UNITS ns ns ns ns 7.6 AC-link Low Power Mode Timing BIT_CLK Stops high in violation of the AC97 specification as noted on the STAC9704/07 errata, but this condition has not caused any known customer problems. Figure 19: AC-link Low Power Mode Timing SYNC BIT_CLK Write to 0x20 Data PR4 Don't care Slot 1 Slot 2 SDATA_OUT SDATA_IN Ts2_pdown Note: BIT_CLK not to scale 37 10/02/98 SigmaTel, Inc. Table 24: AC-link Low Power Mode Timing STAC9704/7 PARAMETER End of Slot 2 to BIT_CLK, SDATA_IN low SYMBOL Ts2_pdown MIN - TYP 14 MAX 15 UNITS us 7.7 ATE Test Mode Figure 20: ATE Test Mode RESET# SDATA_OUT Tsetup2rst Hi-Z SDATA_IN, BIT_CLK Toff Table 25: ATE Test Mode PARAMETER Setup to trailing edge of RESET# (also applies to SYNC) Rising edge of RESET# to Hi-Z delay Notes: SYMBOL Tsetup2rst Toff MIN 15.0 TYP MAX 25.0 UNITS ns ns 1. 2. All AC-link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the trailing edge of RESET# causes STAC9704/7's AC-link outputs to go high impedance which is suitable for ATE in circuit testing. Once either of the two test modes have been entered, the STAC9704/7 must be issued another RESET# with all AC-link signals low to return to the normal operating mode. # denotes active low. 38 10/02/98 SigmaTel, Inc. 8. ELECTRICAL SPECIFICATIONS: 8.1 Absolute Maximum Ratings: Voltage on any pin relative to Ground Operating Temperature Storage Temperature Soldering Temperature Output Current per Pin Vss - 0.3V TO Vdd + 0.3V 0o C TO 70o C -55o C TO +125o C o C FOR 10 SECONDS 260 STAC9704/7 4 mA except Vrefout = 5mA 8.2 Recommended Operating Conditions Table 26. Operating Conditions PARAMETER Power Supplies + 3.3V Digital + 5V Digital + 5V Analog + 3.3V Analog MIN 3.135 4.75 4.75 3.135 0 TYP 3.3 5 5 3.3 MAX UNITS 3.435 5.25 5.25 3.435 70 V V V V oC Ambient Temperature SigmaTel reserves the right to change specifications without notice. 39 10/02/98 SigmaTel, Inc. 8.3 Power Consumption Table 27. Power Consumption PARAMETER Digital Supply Current Analog Supply Current Power Down Status in Sequence PR0 +5V Analog Supply Current PR1 +5V Analog Supply Current PR2 +5V Analog Supply Current PR3 +5V Analog Supply Current PR4 +3.3V Digital Supply Current PR4 +5V Digital Supply Current PR5 No Effect + 5V Digital + 3.3V Digital + 5V Analog + 3.3V Analog MIN TYP 45 4 70 62 58 44 20 0.1 0.1 0.1 STAC9704/7 MAX UNITS mA mA mA mA mA mA mA mA mA mA 8.4 AC-link Static Digital Specifications AVss=DVss=0V; 50pF external load) (Tambient = 25 o C, DVdd = 5.0V or 3.3V 5%, Table 28. AC-link Static Specifications PARAMETER Input Voltage Range Low level input range High level input voltage High level output voltage Low level output voltage Input Leakage Current (AC-link inputs) Output Leakage Current (Hi-Z'd AC-link outputs) Output buffer drive current SYMBOL Vin Vil Vih Voh Vol MIN -0.30 0.40xDVdd 0.50xDVdd -10 -10 4 TYP MAX DVdd + 0.30 0.30xDVdd 0.2xDVdd 10 10 UNITS V V V V V uA uA mA 40 10/02/98 SigmaTel, Inc. 8.5 STAC9704 Analog Performance Characteristics (Tambient = 25 o STAC9704/7 C, AVdd = 5.0V 5%, DVdd = 3.3V 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0dB = 1 Vrms, 10K ohm/ 50pF load, Testbench Characterization BW: 20 Hz - 20kHz, 0dB settings on all gain stages) Table 29. Analog Performance Characteristics PARAMETER Full Scale Input Voltage: Line Inputs Mic Inputs1 Full Scale Output Voltage: Line Output 5V Analog S/N: CD to LINE_OUT 5V Other to LINE_OUT 5V Analog Frequency Response2 Digital S/N D/A 5V A/D 5V Total Harmonic Distortion: Line Output4 D/A & A/D Frequency Response5 Transition Band Stop Band Stop Band Rejection Group Delay Power Supply Rejection Ratio (1kHz) Crosstalk between Input channels Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance Input Capacitance 6 7 3 MIN 90 20 85 75 20 19,200 28,800 +85 10 - TYP 1.0 0.1 1.0 98 98 96 87 +40 +40 +100 1.5 15 MAX 20,000 0.02 19,200 28,800 - - 1 - -70 - - - - UNITS Vrms Vrms dB Hz dB % Hz Hz Hz dB dB ms dB dB dB dB K Ohm pF Out-of-Band Rejection 41 10/02/98 SigmaTel, Inc. Vrefout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift DAC Offset Voltage Deviation from Linear Phase External Load Impedance Mute Attenuation (Vrms input) 10 90 96 100 10 50 1 0.41 x AVdd - 0.5 0.5 STAC9704/7 V dB dB ppm/ o C mV degree K ohm dB Notes: 1. With +20 dB Boost on, 1.0Vrms with Boost off 2. 1 dB limits 3. The ratio of the rms output level with 1 kHz full scale input to the rms output level with all zeros into the digital input. Measured "A weighted" over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 4. 0 dB gain, 20 kHz BW, 48 kHz Sample Frequency 5. 0.25dB limits 6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output. 42 10/02/98 SigmaTel, Inc. 8.6 STAC9704/7 o DVdd = 3.3V 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0dB = 1 Vrms, 10K ohm/ 50pF load, Testbench Characterization BW: 20 Hz - 20kHz, 0dB settings on all gain stages) Table 30. Analog Performance Characteristics STAC9707 Analog Performance Characteristics (Tambient = 25 C, AVdd = PARAMETER Full Scale Output Voltage: Line Inputs to line output 3.3V Line Inputs to LINE_OUT 3.3V @ Line In = 1 Vrms and @ Gain setting of -6 dB Line Inputs to LINE_OUT 3.3V @ Line In = 0.5 Vrms and @ gain setting of 0dB PCM to LINE_OUT 3.3V @ full scale PCM input @PCM gain setting of 0dB PCM to Line Output 3.3V MIC Inputs to LINE_OUT 3.3V @ MIC In = 1 Vrms and @ gain setting of 0dB Analog S/N: CD to LINE_OUT 3.3V Other to LINE_OUT 3.3V Analog Frequency Response2 Digital S/N D/A 3.3V A/D 3.3V Total Harmonic Distortion: Line Output4 D/A & A/D Frequency Response5 Transition Band Stop Band Stop Band Rejection Group Delay Power Supply Rejection Ratio (1kHz) Crosstalk between Input channels 6 3 MIN - TYP 0.5 0.5 0.5 0.5 0.5 MAX - UNITS Vrms Vrms Vrms Vrms Vrms 20 85 75 20 19,200 28,800 +85 - 90 90 90 85 +40 +40 - 20,000 0.02 19,200 28,800 - - 1 - -70 % Hz Hz Hz dB dB ms dB dB Hz Out-of-Band Rejection7 43 10/02/98 SigmaTel, Inc. Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance Input Capacitance Vrefout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift DAC Offset Voltage Deviation from Linear Phase External Load Impedance Mute Attenuation (0 dB) 10 90 96 100 10 10 +100 1.5 15 0.41 x AVdd STAC9704/7 - - - - - 0.5 0.5 50 1 dB dB K Ohm pF V dB dB ppm/ o C mV degree K ohm dB Notes: 1. With +20 dB Boost on, 1.0Vrms with Boost off 2. 1 dB limits 3. The ratio of the rms output level with 1 kHz full scale input to the rms output level with all zeros into the digital input. Measured "A weighted" over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 4. 0 dB gain, 20 kHz BW, 48 kHz Sample Frequency 5. 0.25dB limits 6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output. 44 10/02/98 SigmaTel, Inc. Appendix A SPLIT INDEPENDENT POWER SUPPLY OPERATION STAC9704/7 In PC applications, one power supply input to the STAC9704/7 may be derived from a supply regulator (as shown in Figure 3) and the other directly from the PCI power supply bus. When power is applied to the PC, the regulated supply input to the IC will be applied some time delay after the PCI power supply. Without proper onchip partitioning of the analog and digital circuitry, some manufacturer's codecs would be subject to on-chip SCR type latch-up. SigmaTel's STAC9704/7 specifically allows power-up sequencing delays between the analog (AVddx) and digital (VDddx) supply pins. These two power supplies can power-up independently and at different rates with no adverse effects to the codec. The IC is designed with independent analog and digital circuitry that prevents on-chip SCR type latch-up. 3.3V or 5V +/-10% *AVdd must always be >= DVdd 3.3V or 5V +/-10% 0.1uF 0.1uF 10uF 0.1uF reg 10uF 0.1uF 25 AVdd1 12 P C _B E E P 13 PHONE 14 AUX_L 38 AVdd2 1 DVdd1 9 DVdd2 2 XTL_IN 24.576MHz XTL_OUT 3 33pF 5 SDATA_OUT 33pF 15 AUX_R 16 VIDEO_L SIG M A T E L 6 BIT_CLK 8 SDATA_IN 10 17 VIDEO_R 18 CD_L S T A C 9 7 0 4 /7 SYNC 11 RESET 27 Vref 0.1uF 28 10uF 19 CD_GND 20 CD_R 21 MIC1 22 MIC2 23 35 LINE_OUT_L CAP2 0.1uF Vrefout 32 10uF LINE_IN_L 24 LINE_IN_R LINE_OUT_R 560 to 1000 pF 29 560 to 1000 pF 30 AFILT2 AFILT1 36 37 MONO_OUT AVss1 26 AVss2 42 DVss1 4 DVss2 7 LNLVL_OUT_L 39 LNLVL_OUT_R 41 ** Teminate ground plane as close to power supply as possible NOTE: Pins 31, 33, 34, 40, 43 - 48 are No Connects Brd Analog Gnd Brd Digital Gnd 45 10/02/98 SigmaTel, Inc. Appendix B +5.0V/+3.3V POWER SUPPLY OPERATION NOTES STAC9704/7 The STAC9704 is capable of operating from a single 5V supply connected to both DVdd and AVdd. Even though the STAC9704 has digital switching levels of 0.2Vdd to 0.5Vdd (See AC Link Electrical Characteristics in this data book), we recommend that all digital interface signals to the AC-Link be 5V. If digital interface signals below 5V are used, then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity. The STAC9704 can also operate from a 3.3V digital supply connected to DVdd while maintaining a 5V analog supply on AVdd. On-chip level shifters ensure accurate logic transfers between the analog and digital portions of the STAC9704. If digital interface signals above 3.3V are used (i.e. a +5V AC-Link interface), then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity and to prevent on-chip ESD protection diodes from turning on. (See Appendixes A concerning SPLIT INDEPENDENT POWER SUPPLY OPERATION). The STAC9707 must be run from a 3.3V supply connected to both DVdd and AVdd. If digital interface signals above 3.3V are used (i.e. a +5V AC-Link interface), then appropriate level shifting circuitry must be provided to ensure adequate digital noise immunity and to prevent on-ship ESD protection diodes from turning on. *Always operate the STAC97xx digital supply from the same supply voltage as the digital controller supply. *All the analog inputs must be ac-coupled with a capacitor of 3.3 uF or greater. It is recommended that a resistor of about 47k ohm be connected from the signal side of the capacitor to analog GND as shown below. > 3.3 uF SIGNAL Analog Input 47K *All the analog outputs must be ac-coupled. If an external amplifier is used, make sure that the input impedance of the amplifier is at least 10K ohm and use an ac-coupling capacitor of 3.3 uF. 46 10/02/98 SigmaTel, Inc. - NOTES - STAC9704/7 47 10/02/98 SigmaTel, Inc. - NOTE - STAC9704/7 48 10/02/98 SigmaTel, Inc. For more information, please contact: STAC9704/7 SigmaTel, Inc. 6101 W. Courtyard Dr., Bldg. 1, Suite 100 Austin, Texas 78730 Tel (512) 343-6636, Fax (512) 343-6199 email: sales@sigmatel.com Homepage: www.sigmatel.com 49 10/02/98 |
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